The present invention relates generally to a semiconductor memory apparatus, and more particularly, to a row address decoder and a semiconductor memory apparatus having the same.
A typical dynamic random access memory (DRAM) stores data in a large number of memory cells, with each memory cell having a transistor and a capacitor. Each memory cell is connected to a word line and a bit line where the word line and bit line intersect. When a word line is activated, each memory cell receives data from the bit line or outputs data to the bit line. The word line is divided into a main word line and a sub-word line. A single main word line is connected to a plurality of preset sub-word line drivers (e.g. eight sub-word line drivers). These sub-word line drivers are respectively connected to the sub-word lines. Each sub-word line is directly connected to a plurality of memory cells.
In order to activate the main word line and the sub-word line, the semiconductor memory apparatus includes a row address decoder. The row address decoder decodes a plurality of externally received row addresses. At this time, some of the row addresses (generally, six row addresses) are input into the row address decoder and are used to activate the main word lines (here, 64 main word lines), and the remaining row addresses (generally, three row addresses) are used to activate the main word lines (here, 8 main word lines).
A typical semiconductor memory apparatus requires a test process for testing and guaranteeing the quality of the device after it is designed. During this test process, the data storage capability of the memory cells is also tested. Typically, the data storage capability of the memory cells is tested by: inputting data corresponding to a first logic value (e.g. ‘1’) into all of the memory cells, activating a quarter of the sub-word lines (e.g. if there are 512 sub-word lines 128 of the sub-word lines are activated), inputting data corresponding to a second logic value (e.g. ‘0’) into the activated sub-word lines, and determining whether or not the stored data is lost, which may be caused by the influence of coupling noise, or the like.
However, when the data storage capability of the memory cells is tested according to the method just described, each of the very large number of sub-word lines is activated at the same time, and thus an extensive peak current results. As a consequence, the sub-word line driver realizes a reduction in its ability to drive the sub-word line. For this reason, there is a possibility of an error occurring in the test itself, which results in the test having a reduced reliability. In other words, conventional tests for determining the data storage capability of memory cells have a possibility of failure.